“Data Converters: ADCs” – Prof. Boris Murmann (Stanford University)

145.00

“Mixed-Signal IC Design Course” focusing on Analog-to-Digital Converters (ADCs) covering advanced material on the design of SAR ADCs and Time Interleaved ADC architectures. The afternoon of the second day is devoted to gm/ID-based sizing, based on ISCAS 2015 tutorial: “Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables”.

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Sample Lecture – “Data Converters: ADCs” Course (2015)

Course Outline

This course will cover advanced topics related to integrated CMOS circuit design for data converters. Focus is placed on topics that haven’t received an up-to-date treatment in commonly used textbooks. The specific subjects include fundamentals (design of samplers and comparators, noise analysis) as well as advanced material on the design of SAR ADCs and time interleaved architectures.

The majority of textbook material on analog circuit design is based on the square-law model for MOS transistors. While this model remains useful for teaching, it has become too inaccurate for design in nano-scale CMOS. In circuit simulators, this problem has been solved using complex models equations with hundreds of parameters. Since these descriptions are impractical for manual use, designers tend to shy away from hand-analysis-based optimization and resort to a design style built on iterative and time-consuming “tweaking” in a simulator.

This tutorial presents a systematic design methodology that bridges the gap between simulation, hand analysis and script-based optimization. The approach hinges upon Spice-generated look-up tables containing the transistor’s equivalent model parameters (gm, gds, etc.) across a multi-dimensional sweep of the terminal voltages. We interpret and organize these data based on the transistor’s inversion level, employing gm/ID as a proxy and key parameter for design. This width-independent metric captures a device’s efficiency in translating bias current to transconductance and spans nearly the same range in all modern CMOS processes (~3…30 S/A). When combined with other width-independent figures of merit (gm/Cgg, gm/gds, etc.) thinking in terms of gm/ID (rather than gate overdrive) allows us to study the tradeoffs between bandwidth, noise, distortion and power dissipation in a normalized space. The final bias currents and device sizes follow from a straightforward de-normalization step using the current density ID/W. Since this entire flow is driven by Spice-generated data, we maintain close agreement between the desired specs and the circuit’s simulated performance.

Our tutorial will detail the inner workings of this approach, and showcase its capabilities using a variety of practical examples. These will include the design of low-noise and low-distortion gain stages, operational amplifiers, voltage regulators, etc. In addition, we will present suitable flows for the inclusion of process corners.

Lecture List

Lecture #1 – Sampling Circuits

Lecture #2 – Voltage Comparators

Lecture #3 – Noise Analysis and Simulation in Switched-Capacitor Circuits

Lecture #4 – SAR ADCs

Lecture #5 – Aspects of Time-Interleaved ADC Design

Lecture #6 – Data Converter Performance Trends

Lecture #7 & #8 – Tutorial on gm/ID-based Design (I) & (II)

Features & Format

Format: 8 lectures.

Included: 

  • Course notes (PDF)

About The Presenter

Boris Murmann is a Professor of Electrical Engineering at Stanford University. He joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Since 2004, he has worked as a consultant with numerous Silicon Valley companies.

Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters and custom circuits for statistical inference. In 2008, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits, as well as the Data Converter Subcommittee Chair and the Technical Program Chair of the IEEE International Solid-State Circuits Conference (ISSCC). He is a Fellow of the IEEE.

He has authored/co-authored over 150 publications, including 4 books and 5 book chapters.

IEEE SSCS Magazine