“Power Efficient Data Converters” – Prof. Klaas Bult (TU Delft)

Lecture #1 & #2 – Power-Efficient Residue Amplifiers (I) & (II)
A comprehensive method for power estimation of residue amplifiers is presented. Using this method a definition of power efficiency is given, which subsequently is used to analyze recently published, highly efficient residue amplifiers. Design parameters are identified which have a key influence on the power efficiency and design choices based on power efficiency are discussed. It is shown that the most power efficient residue amplifier topologies share the same core circuit and differ primarily in how this core circuit is driven from the input. Finally, an overview is given of these topologies, ranked on power efficiency.

Lecture #3 – ADC Building Blocks
Most ADCs are built from blocks like comparators, DACs, amplifier and logic. The operation and design of these blocks will be discussed. The core operation will be identified and based on that a fundamental estimate of their power dissipation will be given, based on specifications like dynamic range and sampling frequency. This will be used in the lecture on Energy Efficient Nyquist-Rate ADCs.

Lecture #4 & #5 – Energy-Efficient Nyquist-Rate ADCs (I) & (II)
In large SoC’s Data Converters take a dominant position both from a performance point of view as well as from an energy consumption point of view. The past two decades have shown a strongly intensified search for more power efficient Data Converters, in particular power-efficient Analog-to-Digital converters. This presentation will focus on power efficiency of Nyquist-rate Analog to Digital converters and discuss what has been proposed in open literature to reduce the energy consumption, both from a circuit point of view as well as from an architectural point of view. To get a good grasp of how circuit and architectural choices affect the power consumption, a method will be introduced that allows a quick estimation of the power consumption of an ADC, based on the required SNDR, the sampling frequency, the used technology as well as the chosen ADC architecture and circuit implementations. The proposed method enables a comparison based on these choices and can show what their impact is on the power efficiency, without going through the elaborate design of several architectures. It also shows which recent inventions made a large impact on power efficiency and how these inventions can also be of use in other architectures than the ones they have been introduced in.

Lecture #6 – Embedded ADCs
Systems-on-Chip (SoCs) have been a reality in the past 15 years. Several dozens of different functional blocks are being integrated on a single die, reaching transistor counts of over a billion. From the Analog portion of an SoC the Data Converters are probably the most challenging blocks, often limiting system performance and dominating power dissipation. However, requirements regarding yield, die-size, scalability, noise immunity, power and the fact that logic is almost for free, cause distinct differences between embedded Data Converters and their stand-alone, usually general purpose, counterparts. The presentation describes these differences and provides an overview of the state-of-the-art in embedded Data Conversion.

Lecture #7 & #8 – High-Speed CMOS DACs (I) & (II)
Introduction to high-speed current-steering DACs. The principle of current-steering DACs is extremely simple and a good designer needs to know all error mechanisms. Common error mechanisms will be discussed, with error sources affecting amplitude, timing or the shape of the basic output pulse. The problem of code-dependent output impedance is discussed, including solutions. A state-of-the-art DAC design will be shown, including measurements and comparisons to theory and literature.