“Extreme SAR ADCs” – Prof. Chi-Hang Chan (University of Macau)
€645.00
This cutting-edge course provides an in-depth walkthrough from theoretical to practical considerations on extreme speed SAR ADCs. The participants will be guided from fundamental concepts to state-of-the-art implementations followed by practical case studies, continuously exploring new frontiers to extend present day performance. We will also cover energy-efficiency, robustness, and other important practical considerations throughout this unmissable course. Please see below.
Interview with Prof. Chi-Hang Chan (University of Macau)
Preview Lecture #1 – “Extreme SAR ADCs” Online Course (2024)
Sample Lecture – “Extreme SAR ADCs” Online Course (2024)
Sample Homework #1 – “Extreme SAR ADCs” Online Course (2024)
Sample Homework #5 – “Extreme SAR ADCs” Online Course (2024)
The ever-increasing appetite for higher data-rates, from communication to automotive to industrial to healthcare to cloud computing and AI, is the driving force behind the continued research and development of multi-GSPS SAR-type ADCs at extended resolutions.
This cutting-edge course celebrates twenty years of remarkable Time-Interleaved (TI) SAR ADC architecture innovations and inspired circuit design techniques, since the first ever reported 6-bit 600MSPS TI SAR ADC implementation on 90nm Digital CMOS at ISSCC 2004, by providing an in-depth walkthrough from theoretical to practical considerations on extreme speed SAR ADCs. The participants will be guided from fundamental concepts to state-of-the-art implementations followed by practical case studies, continuously exploring new frontiers to extend present day performance.
The course begins by taking a deep dive into interleaver topologies of massive TI SAR ADCs, discussing non-idealities, design considerations, modeling techniques and detailed case study.
This is followed by paying specific attention to the design challenges and solutions of peripheral blocks that are essential for high-performance massive TI ADCs: the input buffer and reference buffer.
Other key SAR ADC blocks, i.e. extreme sampler, comparator, residue amplifier and clocking, are also examined, progressing from fundamental concepts to advanced techniques followed by comprehensive case studies.
Subsequently, the course explores two architectures renowned for their high-speed and energy-efficiency: SAR and Pipeline-SAR ADCs. The emphasis will be on their high-speed implementation varieties, which are specifically fit for extensive interleaving. Once again, the lectures follow a progression from fundamental concepts to state-of-the-art advancements, summarizing with case studies.
Moving forward, digitally-assisted TI SAR ADCs are presented with an in-depth discussion of inter-channel non-idealities and calibration techniques, including input buffer distortion calibration.
The course will conclude with a discussion of good layout practices, tips and considerations for successful implementation of advanced, extremely high-speed SAR-type ADCs.
The recommended target audience for this course are analog and mixed-signal design engineers looking to get into ADC design as well as those already working with ADCs, interested to learn advanced state-of-the-art ultra-high-speed ADC design techniques. Familiarity with fundamental ADC concepts will be beneficial.
Lecture #1 – Massive Time-Interleaved SAR ADCs – A Deep Dive
Time-Interleaved Non-idealities; Front-End Interleaver Topologies; Modeling; Uncertainties; Case Study.
Lecture #2 – Input Buffer and Reference Buffer – Impairments and Remedies
Distortions; Input Buffer Topologies; Linearization Techniques; Case Study; Reference Ripple; Reference Buffer Topologies; Ripple Suppression Techniques; Case Study.
Lecture #3 – Extreme Samplers and Comparators
Bootstrapped; Dynamic Comparators; Noise; Offset and Metastability.
Lecture #4 – Clocking and Extreme Amplifier Overview
Jitter; Re-timer; Open and Closed-Loop Residue Amplifiers.
Lecture #5 – State-of-the-Art Low-Resolution High-Speed SAR ADCs
Single-bit/cycle; Multi-bit/cycle; DAC; SAR Loop; SAR Logic; Redundancy; Case Study.
Lecture #6 – Extended Resolution and High-Speed: Pipeline-SAR ADCs
Overview; Comparison with SAR ADCs; State-of-the-Art MDACs; Case study.
Lecture #7 – Digitally-Assisted Time-Interleaved SAR ADCs
Offset, Gain, Timing Skew and Input Buffer Distortion Calibration Techniques.
Lecture #8 – High-Speed ADC Design and Verification Practices
Design Flow; Critical Paths; Power/Ground Layout Planning; Case Study.
Duration: 16 hours
Format: 8 x 2-hour recorded lectures including interactive Q&A.
Work: Homework assignments (optional) will consolidate the learning from the lectures.
Included:
- Course notes (PDF)
- Homework assignments (PDF)
- Lecture recordings (8 weeks playback access)
- Course homepage
- Class discussion forum (offline Q&A)
- Recommended reading list
- Extra material
Chi-Hang Chan received the B.S. degree in electrical engineering from University of Washington, Seattle, USA, in 2008, the M.S. and Ph.D. degree from the University of Macau, Macao, China, in 2012 and 2015, respectively.
He was a special scientist at the University of California, Los Angeles, USA, in 2016, working on high performance analog-to-digital converters (ADCs).
Prof. Chan is currently an Associate Professor at the University of Macau, Macao, China, where he leads a large research team, working on various types of ADCs, PLLs, Smart Time-of-Flight and AI. His research interests include high-speed Nyquist, wideband oversampling ADCs, ADC calibrations, ring oscillator-based PLLs, and mixed-signal circuits.
He has published over 100 peer-reviewed papers, including 18 ISSCC papers, 22 JSSC papers, 26 Solid-State conference and VLSI conference papers between 2011-2024.
Dr. Chan is a multi-award winner, including 5-time Macau Science and Technology Development Fund (FDCT) Technological Invention Award for outstanding academic and research achievements in microelectronics. He is the recipient of the Solid-State Circuits Society (SSCS) Pre-doctoral Achievement Award, 2015. His research students have achieved various awards, including the Distinguished Design Award at the IEEE A-SSCC Student Design Contest, 2020.
He is a senior member of IEEE. He serves as a data converter subcommittee TPC member of IEEE A-SSCC 2023 and received SSCS reviewer reward 2023.