“Phase-Locked Loops” – Prof. Woogeun Rhee (Tsinghua University)

The traditional phase-locked loop (PLL) in advanced CMOS technology suffers from poor scalability, loop parameter variability and leakage current problems. Accordingly, diversified PLL architectures such as digital-intensive PLLs and circuit techniques have been recently proposed in consideration of performance, power and cost, thus making it more difficult than ever for circuit designers to choose the right design solution. Indeed, there is a large gap between research-level and product-level architectures for the design of integrated PLLs. This course puts more weight on the latter case, considering robust design in addition to high performance.

The short-course consists of three major parts, covering system perspectives, circuit design aspects, and PLL architectures including fractional-N PLLs, digital-intensive PLLs and advanced PLL architectures suitable for the nanoscale CMOS technologies.

In the first part, system design considerations and PLL fundamentals and characteristics are described in an intuitive way. Several design myths about the PLL are also addressed. Then, system design parameters such as phase noise, spur, random jitter, and deterministic jitter are discussed by considering different application aspects for wireless and wireline systems.

The second part describes the practical design aspects of PLL building blocks including phase detectors, frequency dividers, and voltage-controlled oscillators, putting emphasis on practical design aspects for integrated circuit design.

In the last part, various PLL architectures for different applications are discussed. We begin with fractional-N PLL architectures, move to digital-intensive PLL architectures, and discuss recent advanced PLL architectures.

For each lecture, participants will receive optional homework assignments to encourage them to apply their understanding and experience, thereby further enhancing the learning beyond the lecture material. Some homework assignments may include SPICE simulations, whereas others may consist of circuit design calculations.

This course is primarily intended for analog and mixed-signal IC design engineers seeking top-down understanding of advanced state-of-the-art PLL architectures as well as practical knowledge of PLL circuits. The participants will learn the main building blocks of a modern PLL system and the interaction between them. Familiarity with fundamental PLL concepts will be beneficial.